In the early development of integrate circuits, the trend was toward fabricating chips with finely delineated functions. For example, integrated circuit chips were readily available providing low level digital functions, while another class or family of integrated circuit chips were devoted to linear or analog functions to satisfy other applications. The design and fabrication technology evolved, and continues to do so by integrating high density and more complex digital and analog functions within the respective silicon chips. Not unsurprisingly, the industry demands for the integration of both digital and linear functions on a single chip has been recognized. For optimum electrical performance and efficiency of fabrication, the digital functions tend to be carried out by CMOS structures, while the analog functions tend to be designed around bipolar transistor circuits. The merging of bipolar and CMOS (BICMOS) transistor structures is disclosed in the co-pending application "Merged Bipolar/CMOS Technology Using Electrically Active Trench", by Louis Hutter, Ser. No. 945,796, filed Dec. 22, 1986 and now U.S. Pat. Ser. No. 4,819,052.
The merging of bipolar and CMOS transistor structures into a single integrated circuit process typically involves the addition of missing ingredients to an existing process technology. Conventionally, such integration is carried out by adding CMOS processing steps to an existing bipolar technology, and vice versa. Generally, the merging of such technologies results in an increase in the number of masking operations, as well as a non-optimized process, since the added transistor structures must be integrated into the existing chip fabrication process. It can be appreciated that in merging the bipolar and CMOS technologies in the noted manner, various compromises must be made which necessarily result in inefficient or extended processing, or a corresponding compromise in the device operation.
From the foregoing, it can be seen that a need exists for an improved BICMOS fabrication process which is efficient and easily implemented using current silicon processing equipment and techniques. A further need exists for an improved BICMOS fabricating process and resulting structure, wherein the device construction of the bipolar and CMOS devices is decoupled so that such components can be simultaneously and individually optimized. Yet another need exists for a BICMOS processing technique which minimizes the masking operations by optimizing the self-aligned steps and shared operations in fabricating both the bipolar and CMOS devices. An additional need exists for a BICMOS transistor structure wherein the bipolar devices can be fabricated in a smaller wafer area.